The present invention relates generally to semiconductor fabrication, and more particularly to methods for improving the reliability of 0.25-xcexcm technology semiconductors by alleviating stress in intam otherwise result in the formation of voids in the interconnect lines.
Semiconductor chips or wafers are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
In chips that hold integrated circuits, the individual circuit components are interconnected by conductive elements referred to as xe2x80x9cinterconnect lines.xe2x80x9d These interconnect lines are typically arranged in a multi-layered pattern that is deposited on a semiconductive substrate such as silicon. To insulate the interconnect lines from each other, insulative material is deposited between adjacent interconnect line layers.
With the above in mind, so-called 0.25-micron technology has been developed, in which the distance between adjacent layers of interconnect lines in an integrated circuit on a semiconductor chip is equal to or less than about three-eighths of a micron. With such a small spacing between interconnect lines, which have heights of about 1.1 microns, the size of the circuits on the chip can be reduced to result in the above-noted advantages.
Typically, each electrically conductive interconnect line is made of a xe2x80x9cstackxe2x80x9d of metal layers that typically includes a layer made of aluminum or aluminum alloy, and one or more other metal layers. The aluminum is deposited as a film over the substrate and is then lithographically patterned and chemically etched to form a desired pattern for the circuit""s connector lines. Then, a process referred to as high density plasma (HDP) inter-layer dielectric (ILD) formation is used to fill the gaps between adjacent metal stacks with an electrically non-conductive material. Ordinarily, the ILD deposition step is undertaken at relatively high temperature, incidentally precipitating the formation of an intermetallic structure. In current applications, titanium is commonly used as an underlayer for the aluminum, and the intermetallic structure that forms in such a device is TiAl3. Also, an overlayer that includes TiN anti-reflective coating (ARC) is disposed over the stacks, for lithography purposes.
As understood herein, however, voids caused by hydrostatic stresses undesirably can form in the aluminum, and the voiding of the aluminum can be accelerated by the formation of the intermetallic structure. This is undesirable, because when a void forms in a thin aluminum line, the current path through the line unfortunately is diverted, thereby adversely affecting the reliability of the chip.
The present invention understands that the above-mentioned hydrostatic stresses arise because the thermal expansion coefficient of the aluminum layer is different from the thermal expansion coefficient of the encapsulating ILD and the silicon substrate, both of which mechanically constrain the aluminum. Furthermore, when an intermetallic structure such as TiAl3 is formed, the intermetallic structure can volumetrically contract (by 5.9%, in the case of TiAl3), and the aluminum in the intermetallic structure, which is the most compliant metal in the stack, will consequently absorb the contraction-induced strain and thus have an even higher stress state as a result.
Fortunately, the present invention recognizes that contrary to previous methods, it is possible to anneal the metal stacks prior to ILD deposition in 0.25-xcexcm semiconductors, when only the substrate, and not the ILD, constrains the aluminum in the stacks. As recognized by the present invention, the consequence is that the likelihood of void formation in the interconnect lines is reduced, thereby improving 0.25-xcexcm chip reliability.
A method is disclosed for making a semiconductor chip having electrically conductive interconnect lines. The method includes providing at least one substrate, and establishing at least one predetermined pattern of electrically conductive interconnect lines on the substrate. In accordance with the present invention, prior to depositing a dielectric layer between the interconnect lines, the lines are annealed.
In a preferred embodiment, each line establishes a stack including at least one layer having aluminum therein and at least one layer having titanium therein, and an alloy of titanium and aluminum (i.e., Tixe2x80x94Al) is formed at the beginning of an annealing step, whereby a metal compound (i.e., TiAl3) is formed at the end of the annealing step. Preferably, the annealing step is undertaken by heating the electrically conductive lines to a temperature of between three hundred fifty degrees Celsius and four hundred fifty degrees Celsius (350xc2x0 C.-450xc2x0 C.) for a period of between ten minutes and ninety minutes (10 min-90 min), whereby a compound of titanium and aluminum results (i.e., TiAl3). Moreover, the electrically conductive lines are exposed to one or more annealing gases, including nitrogen and hydrogen, during the annealing step. In one preferred embodiment, the ILD is TEOS that is deposited by directing TEOS onto the lines while simultaneously removing excess TEOS by sputtering. A chip made according to the present method, and a computing device incorporating the chip, are also disclosed.
In another aspect, a semiconductor chip includes at least one substrate and at least one predetermined pattern of aluminum lines supported by the substrate, with adjacent lines being separated by distances equal to or less than about three-eighths of a micron. An alloy of aluminum and titanium is on the lines, with the Tixe2x80x94Al alloy having been reacted, thereby forming the TiAl3 compound prior to insulating the lines from each other.
In still another aspect, a method for making a semiconductor chip includes establishing plural electrically conductive lines on at least one substrate. At least first lines are separated from second lines by distances equal to or less than three-eighths of a micron. The method further includes reacting a metal alloy on the lines, thereby forming the metal compound and, after reacting the alloy to form the metal compound, depositing a dielectric between at least two lines that are adjacent each other. With this method, the dielectric does not constrain the lines during the reacting step.
Other features of the present invention are disclosed or apparent in the section entitled: xe2x80x9cDETAILED DESCRIPTION OF THE INVENTIONxe2x80x9d